2. IP 核
  3. D68000-BDM

D68000-BDM

要求信息

产品描述

D68000-BDM soft core is binary-compatible with an industry-standard 68000 32-bit microprocessor. It has a 16-bit data bus and a 24-bit address data bus. Of course, the code is compatible with MC68008, upward compatible with MC68010 virtual extensions, and MC68020 32-bit implementation of the architecture. Our efficient IP Core has an improved instruction set, which allows the execution of the program with higher performance than a standard 68000 core. D68000-BDM is delivered with a fully automated test bench and complete set of tests, allowing easy package validation at each stage of the SoC design flow.

You might also like: - D68000-CPU32 - https://www.dcd.pl/product/d68000-cpu32-2/ - D68000-CPU32+ - https://www.dcd.pl/product/d68000-cpu32-plus/

主要特性与优势

  • USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available
  • Static synchronous design
  • Fully synthesizable
  • M6800 family synchronous interface: 3- and 2- wire bus arbitration; Supervisor and user modes
  • Memory interface includes: Up to 4 GB of address space; 16-bit data bus; Asynchronous bus control
  • Interrupt controller: 7 priority levels interrupt controller; Unlimited number of virtual interrupt sources; Vectored and auto-vectored modes
  • Arithmetic Logic Unit includes: 8,16,32-bit arithmetic & logical operations; 16×16 bit signed and unsigned multiplication; 32/16 bit signed and unsigned division; Boolean operations
  • 5 data types supported: bits; BCD; bytes, words and long words
  • Immediate data: Immediate; Quick immediate
  • Absolute data: Absolute short; Absolute long
  • PC relative: Relative with offset; Relative with index and offset
  • Indirect: Register indirect; Postincrement register indirect; Predecrement register indirect; Register indirect with offset; Indexed register indirect with offset
  • Direct: Data register direct; Address register direct
  • 14 addressing modes:
  • 32 bit data and address registers
  • Bus cycle timings identical to 68000
  • Shorter effective address calculation time
  • Idle cycles removed to improve performance
  • Optimized shifts and rotations
  • DIVS, DIVU take 28 clock periods
  • MULS, MULU take 28 clock periods
  • Software compatible with 68000 industry standard

特色技术文档

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证？ 片 LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K70T -1 Vivado ML 2023.2 Y 1265 5724 0 0 0 0 100
VIRTEX-7X Family XC7VX330T -3 Vivado 2019.1 Y 2710 7020 0 0 0 0 101
Zynq-7000 Family XC7Z010 -3 Vivado 2019.1 Y 1867 6725 0 0 0 0 115

IP 质量指标

综合信息

数据创建日期 Jan 24, 2024
当前 IP 修订号 1.22
当前修订日期已发布 Jan 18, 2016
第一版发布日期 Jun 17, 2003

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 5
可否提供参考？ N

交付内容

可供购买的 IP 格式 Netlist, Source Code
源代码格式 VHDL, Verilog
是否包含高级模型？ N
提供集成测试台 Y
集成测试台格式 VHDL, Verilog
是否提供代码覆盖率报告？ Y
是否提供功能覆盖率报告？ N
是否提供 UCF？ UCF
商业评估板是否可用？ N
是否提供软件驱动程序？ Y
驱动程序的操作系统支持 -

实现方案

代码是否针对 Xilinx 进行优化？ N
定制 FPGA 优化技术 -
所支持的综合软件工具及版本 Xilinx XST; Synplicity Synplify; Mentor Precision
是否执行静态时序分析？ Y
是否包含 IP-XACT 元数据？ N

验证

是否有可用的文档验证计划？ Executable and documented plan
测试方法 Both
断言 N
收集的覆盖指标 Code, Functional, Assertion
是否执行时序验证？ Y
可用的时序验证报告 Y
所支持的仿真器 Cadence NC-Sim; Cadence IUS; Mentor ModelSIM

硬件验证

在 FPGA 上进行验证 Y
所使用的硬件验证平台 FPGA
已通过的行业标准合规测试 N
特定的合规测试 own
测试日期 Jun 16, 2003
是否提供测试结果？ Y