NVMe to NVMe Bridge

  • 产品编号: IPC-NV171A-BR
  • 供应商: IntelliProp Inc.
  • Partner Tier: Elite Certified

产品描述

The IntelliProp NVMe Bridge, IPC-NV171A-BR, utilizes the IntelliProp NVMe Host Core and the IntelliProp NVMe Device Core to create an NVMe protocol bridge. The bridge communicates with an NVMe host and an NVMe device. Throughout this document, these components of the system are referred to as the NVMe host and the NVMe device. The bridge also contains an NVMe host and NVMe device. These components are referred to as the Bridge NVMe host and the Bridge NVMe Device.


主要特性与优势

  • Data Command Handling – When the NVMe host requires a read or write command to an NVMe device, commands are written to host system memory dedicated to storing the command structure.
  • Data Command Completion Handling – When the NVMe device has completed a data command, a completion is posted back to the bridge.
  • Read Data Payload Transfer – The NVMe device will transfer frames of data to the bridge via the PCIe link when processing a read command
  • Write Data Payload Transfer – The NVMe device will initiate a data transfer from the bridge to the device via the PCIe link when processing a write command
  • Command and Data Ordering – The order of payload data transfers and command completions is established by the NVMe device
  • Physical Region Page list transfer – For commands that utilize a sector count large enough to require more than two data packets, the NVMe device will initiate a data transfer from the bridge to retrieve additional Physical Region Page descriptor entries.
  • Non data command handling – Non data commands include but are not limited to Flush Cache, Write Correctable, Compare and Dataset Management, as well as all administrative commands defined in the NVMe specification
  • Error Handling – Hardware asserts logic for processor to complete the error handling

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU9P -2 Vivado ML 2022.2 Y 32661 153499 369 15 0 8 250
Zynq-UP-MPSoC Family XCZU19EG -2 Vivado ML 2022.2 Y 32843 154053 361 15 0 8 250
Kintex-UP Family XCKU11P -2 Vivado ML 2022.2 Y 33033 154950 356 15 0 8 250
VERSAL_AI_CORE Family XCVC1902 -2 Vivado ML 2022.2 Y 32290 151462 557 6 0 8 250

IP 质量指标

综合信息

数据创建日期 May 24, 2023
当前 IP 修订号 1.84c
当前修订日期已发布 May 01, 2023
第一版发布日期 May 01, 2016

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 6
可否提供参考? N

交付内容

可供购买的 IP 格式 Netlist
源代码格式 Verilog
是否包含高级模型? N
提供集成测试台 N
是否提供代码覆盖率报告? N
是否提供功能覆盖率报告? N
是否提供 UCF? SDF
商业评估板是否可用? Y
评估板所用的 FPGA Zynq UltraScale+ MPSoC
是否提供软件驱动程序? N
驱动程序的操作系统支持 Yes

实现方案

代码是否针对 Xilinx 进行优化? N
定制 FPGA 优化技术 None
所支持的综合软件工具及版本 Other
是否执行静态时序分析? Y
AXI 接口 AXI4, AXI4-Lite
是否包含 IP-XACT 元数据? Y

验证

是否有可用的文档验证计划? Yes, document only plan
测试方法 Both
断言 N
收集的覆盖指标 None
是否执行时序验证? Y
可用的时序验证报告 N
所支持的仿真器 Mentor Questa

硬件验证

在 FPGA 上进行验证 Y
所使用的硬件验证平台 Kintex Ultrascale
已通过的行业标准合规测试 N
是否提供测试结果? N