AVB/Automotive Ethernet Switch IP Core

  • 产品编号: S-3133
  • 供应商: SoC-e
  • Certified Partner

产品描述

AVB/Automotive Ethernet Switch (AVBES) IP Core implements an Ethernet switch which supports all AVB conforming standards. It can be implemented optimally depending on the application, from a simple 2-ports end-point to a complex multiport switch.

The current release of AVBES IP supports 802.1AS for timing and synchronization, 802.1Qav allowing credit-based shaper traffic and strict priority traffic. In order to manage network resources, AVBES supports also 802.1Qat, Stream Reservation Protocol.

AVBES IP can be optimally implemented on Xilinx SoC devices. As an example, targeted devices are Xilinx Zynq-7000 SoC and Zynq Ultrascale+ MPSoC. These powerful platforms offer combined hardware and software processing capabilities and they ensure upgradeability of the solution thanks to their reconfigurable nature.

AVBES IP can be evaluated using the AVBES Kit and can be combined with SoC-e Multiport FMC Board to offer a complete solution to automotive market.


主要特性与优势

  • Broadcast/Multicast Storm Protection
  • Configurable 3 to 32 Ethernet ports
  • Different data rate (10/100/1000 Mbps) for each port
  • Dynamic MAC Table with automatic MAC addresses learning and aging (up to 4096 entries)
  • Full-Duplex Ethernet 10/100/1000
  • IEEE 802.1AS for Time Synchronization Layer
  • IEEE 802.1Qat for Stream Reservation Protocol (SRP) - Network resources management
  • IEEE 802.1Qav for Forwarding and Queuing for Time-Sensitive Streams (FQTSS) - Credit Based Shaper: Configurable bandwidth reservation for each traffic class
  • Jumbo Frame Management
  • MDIO, UART, AXI4-lite or CoE (Configuration-over-ethernet) management interfaces
  • MII/RMII/GMII/RGMII/SGMII/QSGMII/USXGMII interfaces for attaching to an external Physical Layer device (PHY)
  • Port-based VLAN support
  • Static MAC Table (up to 4096 entries)
  • Full-duplex 2.5/5/10 Gbps Ethernet Uplink Interfaces
  • Per-Port Rate limiting (Broadcast, Multicast and Unicast traffic)

特色技术文档

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-7000 Family XC7Z020 -1 Vivado 2018.3 6072 16418 72 0 0 0 125

IP 质量指标

综合信息

数据创建日期 Oct 11, 2021
当前 IP 修订号 18.11
当前修订日期已发布 Oct 31, 2018
第一版发布日期 Oct 29, 2018

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 1
可否提供参考? N

交付内容

可供购买的 IP 格式 Netlist, Source Code
源代码格式 VHDL
是否包含高级模型? N
提供集成测试台 N
是否提供代码覆盖率报告? N
是否提供功能覆盖率报告? N
是否提供 UCF? XDC
商业评估板是否可用? Y
评估板所用的 FPGA Zynq-7000
是否提供软件驱动程序? Y
驱动程序的操作系统支持 Yes (Linux)

实现方案

代码是否针对 Xilinx 进行优化? N
定制 FPGA 优化技术 None
所支持的综合软件工具及版本 Vivado Synthesis / 2015.4; Vivado Synthesis / 2017.2
是否执行静态时序分析? Y
AXI 接口 AXI4-Stream, AXI4-Lite
是否包含 IP-XACT 元数据? Y

验证

是否有可用的文档验证计划? No
测试方法 Directed Testing
断言 N
收集的覆盖指标 Functional
是否执行时序验证? Y
可用的时序验证报告 Y
所支持的仿真器 Xilinx lSim

硬件验证

在 FPGA 上进行验证 Y
所使用的硬件验证平台 SMARTzynq/SMARTmpsoc
已通过的行业标准合规测试 N
是否提供测试结果? N