Serial RapidIO LogiCORE IP



LogiCORE™ IP Serial RapidIO v5.6 – SRIO Gen 1.3 (with extensions for Gen 2 -5G line rate) Support
For the Serial RapidIO Gen 2 Xilinx LogiCORE IP, please click here.

The LogiCORE IP Serial RapidIO Endpoint solution, designed to RapidIO Gen 1.3 specification with Gen 2 -5G line rate support, comprises of a highly flexible and optimized Serial RapidIO Physical Layer core and a Logical (I/O) AND Transport Layer core. 设计此内核的目的是为了确保时序的可预测性,从而可大幅降低工程设计时间的投入,并将资源主要应用于用户特定的应用逻辑中。

The RapidIO Logical (I/O) and Transport Layer core and the RapidIO Physical Layer core, provide a complete Serial RapidIO protocol stack.  Additionally, a highly optimized and configurable buffer design is included with these cores to implement a Serial RapidIO endpoint. While a modular IP design approach provides flexibility to enable ease of customization, the Xilinx tool chain automates generation of the serial endpoint on an FPGA by using these building block IP cores through a configurable and easy-to-use graphical user interface.


  • 1x & 4x Serial PHY - Supports Virtex-6 LXT/SXT/HXT, Spartan-6 LXT, Virtex-5 LXT/SXT/FXT, and Virtex-4 FX FPGAs
  • 1x & 4x Serial PHY - Supports 1.25, 2.5, 3.125, 5.0 Gpbs line speed
  • 1x & 4x Serial PHY - 64-bit internal data path
  • 支持数据包重试、stomp、传输错误恢复、基于节流阀的流量控制和 CRC
  • 为所有外发的数据包提供 8/16 位器件 ID、可编程源 ID 支持
  • Doorbell and message support
  • 支持基于优先级的重新发送抑制
  • Independently configurable TX and RX buffer depths





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