纠错 IP

The solution from Creonic for data rates of up to 1 Gbit/s offers outstanding efficiency in terms of implementation complexity.

This LDPC IP core consists of an LDPC encoder and FAID™ decoder achieving a maximum decoding throughput of 1.7Gbytes/s for NAND flash controllers supporting the next generation of NAND flash memories.

5G NR LDPC Decoder IP Core

5G NR LDPC Encoder IP Core

5G NR Rate Matching IP Core

5G NR Rate Recovery IP Core

This LDPC IP core consists of an LDPC encoder and FAID™ decoder achieving a maximum decoding throughput of 6.5Gbytes/s for NAND flash controllers supporting the next generation of NAND flash memories.

LogiCORE™ IP Convolutional Encoder 核可用于各种广泛的纠错应用，通常用于 Viterbi 解码器。

DVB-RCS2 (Digital Video Broadcast – Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digital data transmission via satellites.

DVB-RCS2 Turbo Decoder IP Core

The Creonic DVB-S2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder).

The Creonic DVB-S2X decoder is a scalable solution that allows for symbol rates of up to 100 MSymb/s on state-of-the-art AMD FPGAs.

The Creonic DVB-S2X high performance multi-carrier demodulator performs all tasks of an inner receiver

IntelliProp’s IPC-BL119A-ZM is a highly configurable core that provides a method of extending an information block with extra bits to guard against the loss or corruption of data across noisy or unreliable communication channels.

The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GMR Release 2 (GMPRS-1) and use LDPC codes for the first time.

Interleaver/De-interleaver LogiCORE 模块是一款高速、紧凑型设计，其使用单个时钟，支持全面同步。这是一个参数化特性，支持 Forney 卷积架构和矩形块架构。分支数量与分支长度均为参数化。该内核支持从 1 到 256 位的符号大小。

Reed-Solomon 编码器和解码器通常用于数据传输和存储应用，如广播设备、无线局域网、有线电视调制解调器、xDSL、卫星通信、微波网络和数字电视等。

This high performance, fully programmable Reed Solomon Decoder IP Core is intended for use in a wide range of applications requiring forward error correction.

The Reed-Solomon Encoder LogiCORE module is a high speed, compact design that implements many different Reed-Solomon coding standards

This high performance, fully programmable Reed Solomon Encoder IP Core.

The Creonic Ultra-fast BCH Decoder is capable of processing an entire BCH codeword per clock cycle in a pipelined way. Therefore, it achieves outstanding data rates.

该版本的涡轮卷积编码器旨在达到 3GPP 规范。

Viterbi Decoders are used in systems where data are transmitted and subject to errors before reception.