The XPS Central DMA Controller provides simple Direct Memory Access (DMA) services to peripherals and memory devices on the PLB. The controller transfers a programmable quantity of data from a source address to a destination address without processor intervention.
Key Features and Benefits
Connects as a 32-bit master/slave on PLB V4.6 buses of 32, 64 or 128 bits
Provides a single physical channel of Direct Memory Access between a source address and a destination address
Provides programmable registers for source address, destination address and transfer length
Supports different clock domains for Master and Slave interfaces
Supports setting up of source and destination addresses as incrementing or fixed (keyhole)