Versal AI Engine Development using Vitis Model Composer
Vitis™ Model Composer enables the rapid simulation, exploration, and code generation of algorithms targeted for Versal AI Engines from within the Simulink environment. You can achieve this by using the AI Engine library blocks or by importing kernels and data-flow graphs into Vitis Model Composer as blocks and controlling the behavior of the kernels and graphs by configuring the block GUI parameter. The tool also allows you to model and simulate a design with a mix of AI Engine and Programmable logic (HDL/HLS) blocks. Simulation results can be visualized by seamlessly connecting Simulink source and sink blocks with Vitis Model Composer AI Engine blocks.
Vitis Model Composer provides a set of performance-optimized blocks for use within the Simulink environment. These include:
AI Engine blocks
HLS (Targeting PL and generates HLS code)
HDL (Targeting PL and generates RTL code)
Learn to program Versal AI Engines using Vitis Model Composer
This 20-minute video shows how the Simulink tool and Vitis Model Composer can be used to model, simulate, and optimize a FIR filter on an AI Engine array.
Explore design examples on how to use Vitis Model Composer blocks
|Importing Kernels and Graphs||Run time parameters (RTP)||DSP Functions|
|Importing a kernel class as a block||A design with a scalar RTP input||Filtering in frequency domain|
|Importing a graph as a block||A design with an asynchronous vector RTP input||Stream based FFT running at 2 GSPS|
|FIR with 4Gsps throughput|
|Dual stream SSR FIR at 16 GSPS|
|Dynamic Point FFT|
Access tutorials on AI Engine Library, HLS and HDL
This live online course provides experience with using the Vitis™ Model Composer tool for model-based designs.
Explore the Github repository to learn more about rapid design using Vitis™ Model Composer.