NVMe Streamer

产品描述

NVMe (Non-Volatile Memory Express) has become the prominent choice for connecting Solid-State Drives (SSD) when storage read/write bandwidth is key. Electrically, the NVMe protocol operates on top of PCIe; it leaves behind legacy protocols such as AHCI, and thus scales well for performance.

MLE has been integrating PCIe, and NVMe, into FPGA-based systems for a while. Now, MLE releases NVMe Streamer which is a so-called Full Accelerator NVMe host subsystem integrated into FPGAs, and most prominently into AMD Zynq Ultrascale+ MPSoC and RFSoC devices.

MLE's new NVMe Streamer is the result of many successful customer projects and responds to the embedded market's needs to make use of modern SSDs. NVMe Streamer is a fully integrated and pre-validated subsystem stack operating the NVMe protocol fully in Programmable Logic (PL) with no software running, keeping the Processing System (PS) out of this performance path. For AMD FPGAs, NVMe Streamer utilizes AMD GTH and GTY Multi-Gigabit Transceivers together with AMD PCIe Hard IP Cores for physical PCIe connectivity.


主要特性与优势

  • Scalable to PCIe x1, x2, x4, x8 lanes.
  • Compatible with PCIe Gen 1 (2.5 GT/sec), Gen 2 (5 GT/sec), Gen 3 (8 GT/sec), Gen 4 (16 GT/sec) speeds.
  • Approx. 50k LUTs and 170 BRAM tiles (for AMD UltraScale+).
  • Control & Status interface for IO commands and drive administration.
  • PCIe Enumeration, NVMe Initialization & Identify, Queue Management.
  • Fully integrated and tested NVMe Host Controller IP Core.
  • Full Acceleration means "CPU-less" operation.
  • Provides one or more NVMe / PCIe host ports for NVMe SSD connectivity.

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU7EV -2 Vivado ML 2023.1 Y 0 5277 201 9 20 4 250

IP 质量指标

综合信息

数据创建日期 Dec 05, 2023
当前 IP 修订号 2023.2
当前修订日期已发布 Sep 22, 2023
第一版发布日期 Feb 21, 2020

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 6
可否提供参考? Y

交付内容

可供购买的 IP 格式 Netlist, Source Code, Bitstream
源代码格式 Verilog, VHDL
是否包含高级模型? N
提供集成测试台 Y
集成测试台格式 Other
是否提供代码覆盖率报告? N
是否提供功能覆盖率报告? N
是否提供 UCF? XDC
商业评估板是否可用? Y
评估板所用的 FPGA Zynq UltraScale+ MPSoC
是否提供软件驱动程序? N

实现方案

代码是否针对 Xilinx 进行优化? Y
标准 FPGA 优化技术 Instantiation, UltraFast Design Methodology, Other Optimization Techniques
定制 FPGA 优化技术 None
所支持的综合软件工具及版本 Vivado Synthesis / 2018.1
是否执行静态时序分析? Y
AXI 接口 AXI4-Stream, AXI4-Lite
是否包含 IP-XACT 元数据? Y

验证

是否有可用的文档验证计划? Yes, document only plan
测试方法 Constrained random testing
断言 N
收集的覆盖指标 Functional
是否执行时序验证? N
可用的时序验证报告 N
所支持的仿真器 Xilinx lSim / 2018.1; Mentor Questa

硬件验证

在 FPGA 上进行验证 Y
所使用的硬件验证平台 ZCU106
已通过的行业标准合规测试 N
是否提供测试结果? N