DisplayPort 产品和软件需求

Hardware Evaluation Time Out Period * : ~ 2-3 hrs

软件需求清单

LogiCORE™ 版本 支持 AXI4 软件支持 支持的器件系列
v1.0 v2.1 AXI4-LITE
AXI4-Stream
Vivado® 2019.2 Kintex® UltraScale+™
Virtex® UltraScale+
Zynq® UltraScale+
Kintex UltraScale™
Virtex UltraScale
DisplayPort RX/TX Subsystem v2.1 AXI4-LITE
AXI4-Stream
Vivado 2019.1 Kintex UltraScale+
Virtex UltraScale+
Zynq UltraScale+
Kintex UltraScale
Virtex UltraScale
Zynq-7000
Artix®-7
Kintex-7
Virtex-7
HDCP 1.x v1.0 AXI4-LITE
AXI4-Stream
Vivado 2019.2 Kintex UltraScale+
Virtex UltraScale+
Zynq UltraScale+
Kintex UltraScale
Virtex UltraScale
Zynq-7000
Artix®-7
Kintex-7
Virtex-7
Video PHY Controller
v2.2 AXI4-Lite
AXI4-Stream
Vivado 2019.2 Kintex UltraScale+
Virtex UltraScale+
Zynq UltraScale+
Kintex UltraScale
Virtex UltraScale
Zynq-7000
Artix-7
Kintex-7
Virtex-7
DisplayPort v7.0 AXI4-Lite
AXI4-Stream
Vivado 2017.1 Kintex UltraScale
Virtex UltraScale
Zynq-7000
Artix-7
Kintex-7
Virtex-7
DisplayPort v3.2 AXI4-Lite
AXI4-Stream
ISE® 14.2 Artix-7
Kintex-7
Virtex-7
Virtex-6 HXT / SXT / LXT
Spartan®-6 LXT
带有辅助音频和 SPDI 接口的 DisplayPort v1.1 AXI4-Lite ISE 14.1 Artix-7
Kintex-7 / -2L
Virtex-7 / -2L
Virtex-6 LXT / SXT / HXT
Spartan-6

Download the required software from the Xilinx.com Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.

* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.

The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.