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JESD204 产品和软件需求

Hardware Evaluation Time Out Period * : ~ 2-3 hrs

软件需求表

LogiCORE™ 版本 AXI4 支持 软件支持 支持的器件系列
JESD204 PHY v4.0    Vivado® 2017.3 Kintex® UltraScale+™
Virtex® UltraScale+
Zynq® UltraScale+
Kintex UltraScale™
Virtex UltraScale
Zynq-7000
Artix®-7
Kintex-7
JESD204C v4.1 AXI4-Stream
AXI4-Lite
Vivado 2019.1 Kintex UltraScale+
Virtex UltraScale+
Zynq UltraScale+
Kintex UltraScale
Virtex UltraScale
JESD204 v7.2 AXI4-Stream
AXI4-Lite
Vivado 2017.3 Kintex UltraScale+
Virtex UltraScale+
Zynq UltraScale+
Kintex UltraScale
Virtex UltraScale
Zynq-7000
Artix-7
Kintex-7
Virtex-7
JESD204 v3.2 AXI4-Stream
AXI4-Lite
ISE® 14.6 Zynq-7000
Kintex-7
Virtex-7
Virtex-6 HXT / SXT / LXT

Download the required software from the Xilinx.com Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.

* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.

The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.

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