本文概述了赛灵思 Virtex-5 器件的功能特性和产品选择。

This overview outlines the features and product selection of the Xilinx Virtex-5 devices.

The LogiCORE IP 10-Gigabit Ethernet MAC core is a single-speed full-duplex 10-Gb/s Ethernet Media Access Controller (MAC) solution that enables the design of high-speed Ethernet systems and subsystems.

Specifies the electrical characteristics of the Virtex-5 family of FPGAs, including absolute maximum ratings, recommended operating conditions, supply requirements, and switching characteristics.

The LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII core provides a flexible solution for connection to an Ethernet Media Access Controller (MAC) or other custom logic and supports two standards of operation that can be dynamically selected.

This is the data sheet for the CAN v3.2 core.

The eXtended Attachment Unit Interface (XAUI) core is a high-performance, low-pin count 10-Gb/s interface intended to allow physical separation between the data link layer and physical layer devices in a 10-Gigabit Ethernet system. The XAUI core implements a single-speed full-duplex 10-Gb/s Ethernet eXtended Attachment Unit Interface (XAUI) solution for the Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-4, and Spartan-6 Field Programmable Gate Array (FPGA) devices.

The LogiCORE IP Fibre Channel Core provides a flexible core for use in any non-loop FC port and can run at 1, 2, and 4 Gbps. The FC core includes credit management features as well as the FC (old) Port State Machine for link initialization.

This is the data sheet for 3GPP2 Turbo Decoder v2.1.

The LogiCORE IP Tri-Mode Ethernet Media Access Controller (TEMAC) solution comprises the 10/100/1000 Mbps Ethernet MAC, 1 Gbps Ethernet MAC and the 10/100 Mbps Ethernet MAC IP core. All cores support half-duplex and full-duplex operation.

The LogiCORE IP Ethernet Statistics core provides a user-configurable collection of statistical counters that can be used to gather network traffic statistics for Xilinx Ethernet Media Access Controller (MAC) products.

The Xilinx Floating-Point core provides designers with the means to perform floating-point arithmetic on an FPGA device. The core can be customized for operation, word length, latency, and interface.

MPEG-4 Part 2 Simple Profile Decoder core is a fully functional VHDL design implemented on a Xilinx FPGA. The MPEG-4 Decoder core accepts compressed video information and recreates a video image suitable for display.

This is the data sheet for the PLBV46 to OPB Bridge (v1.00a) core

The Xilinx DVB-S.2 FEC Encoder core provides designers with a Forward Error Correction (FEC) Encoding block for DVB-S.2 systems.

The MPEG-4 Part 2 Simple Profile Encoder core is a fully functional VHDL design implemented on a Xilinx FPGA.

The Interrupt Control service provides interrupt capture support for internal IPIF sub-block, as well as support for the connected IP function.

The MPEG-4 Part 2 Simple Profile Decoder core is a fully functional VHDL design implemented on a Xilinx FPGA.

The MPEG-4 Part 2 Simple Profile Encoder core is a fully functional VHDL design implemented on a Xilinx FPGA.

This is the data sheet for the 802.16e CTC Encoder v3.0 core

The LogiCORE IP Aurora 64B/66B core implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex-5 FXT and TXT and Virtex-6 LXT, SXT, and HXT devices.

The LogiCORE IP Divider Generator core v3.0 creates a circuit for integer division based on Radix-2 non-restoring division, or High-Radix division with prescaling.

The Xilinx 128-bit Processor Local Bus (PLB) v4.6 provides bus infrastructure for connecting an optional number of PLB masters and slaves into an overall PLB system. It consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units, as well as an optional DCR (Device Control Register) slave interface to provide access to its bus error status registers.

This is the data sheet for Virtex-5 LogiCORE Endpoint Block for PCI Express.

This is the data sheet for Virtex-5 GTP Aurora 2.8 core.

This document defines the functional operation of the PLBv46 Root Complex and Endpoint Bridge for PCI Express, hereafter called PLBv46 Bridge. The PLBv46 Bridge is an interface between the Processor Local Bus (PLB) and the PCI Express (PCIe) bus.

The LogiCORE IP Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode Ethernet MAC (Ethernet MAC) in Virtex-5 LXT, SXT, FXT and TXT FPGAs using the Xilinx CORE Generator software.

The PLBV46 Master Burst is a continuation of the Xilinx family of IBM CoreConnect compatible LogiCORE products. It provides a bi-directional interface between a User IP core and the PLB v4.6 bus standard. This version of the PLBV46 Master Burst has been designed for PLBV46 Master operations consisting of single data beat read or write transfers and Fixed Length Burst Transfers of 2 to 16 data beats.

The XPS Universal Asynchronous Receiver Transmitter (UART) Lite Interface connects to the PLB (Processor Local Bus) and provides the controller interface for asynchronous serial data transfer. This soft IP core is designed to interface with the PLBV46.

This is the data sheet for the H.264 Deblocker Core v1.0 core.