接口 IP

10G Managed Ethernet Switch (MES) IP core implements a low-latency HOL-efect free crossbar matrix that allows continuous transfers al full-speed. It supports up-to 32 ports at 100M/1G/2.5G/5G/10G.

TOE25G-IP core is high performance, full TCP/IP stack implementation by pure hardwired logic without CPU. Enabling 25G TCP transmission at maximum performance without bottleneck from Host systems.

Designed to optimise display colours in real time, this IP Core uses Tetrahedral Interpolation to maximise screen performance using a 3D LUT for video workflows. Easy integration using AMD Vivado IP

NR3D is a circuit for reducing temporal noises with use of frame memory. Suppresses noises while suppressing motion artifacts.

The core is a UDP/IP hardware protocol stack. Designed for standalone operation, the core offloads the host processor from the task of UDP/IP encapsulation and enables media streaming with speeds up to 40Gbps even in processor-less designs. Trouble-free operation is ensured through run-time programm...

H.264 4K video decoder IP Core

H.264 4K Video Encoder

The 80188EB is a powerful 16-bit microprocessor core, executes the instruction list compatible with 80188EB microprocessor.

BADGE provides graphics acceleration for drawing common graphical shapes, such as lines, rectangles, text and copying rectangles (BitBLT) between different locations on screen. BADGE includes a number of GPUs (Graphics Processing Units). These work in parallel for generating the accelerated graphics...

The IntelliProp IPC-BL204-ZM is an AES-CTR Counter Mode Encryption Core supporting 128 or 256 bit encryption. The IPC-BL204-ZM provides encryption/decryption based on a design principle known as substitution-permutation network (SP-network). An SP-network takes a block of the plaintext (clear data o...

Logic Fruit Technologies has designed & implemented ARINC 818 Transmitter & Receiver IP Core supporting multiple line rates up to 4.25Gbps. The IP core has been developed by taking DO-254 Methodology

The ARINC 818 IP Core is a protocol standard offering high-bandwidth, low latency, uncompressed digital video transmission.

ARINC 818 is a point-to-point, serial protocol, high bandwidth, low latency protocol for transmission of uncompressed video up to 4K, audio and data during blanking period, widely used in AVIONICS. Since a vast portion of the newer applications of the ARINC 818-2 have several displays with many chan...

ARINC 818-3 IP Core offers higher data rates up to 28Gbps and 64B/66B encoding for high-speed avionics video.

The New Wave Design and Verification (New Wave DV) ARINC-818 core provides a complete hardware IP solution for the ARINC-818 protocol. The core provides full specification compliance, hardware-based container processing, and offload of frame handling including: ARINC-818 Container offload, hardwar...

技术支持 器件系列: Virtex UltraScale+ Kintex UltraScale+ Zynq UltraScale+ MPSoC ... Zynq-7000 Virtex-7 ... Artix-7 Versal AI Core Series Versal Prime Series

LogiCORE™ Audio Clock Recovery Unit 核是一款 Xilinx 软 IP 核，可与 Vivado™ Design Suite 配合使用。它提供一个简单的机制，从给定的参考时钟恢复音频采样时钟。它可与 HDMI 或 DisplayPort 接收器一起使用，以恢复音频采样时钟。

在 S2MM 中某些通道的采样丢失时，支持 pad 0’s 可在 S2MM 的输入流中处理音频通道的随机顺序 在停止及软复位时，成功完成命令。 ... Virtex-7

Auto Contrast Enhancement (ACE) IP enhanced the contrast of input stream without loss of input image details. This IP is targeted for Thermal Imaging, Bio-Medical Imaging & Machine Vision Application.

AGC IP core takes camera streams from the source and automatically calculate the alpha and beta values and generate output according to those alpha & beta. This IP is part of Computer Vision Pipeline.

The AXI Block Sum core takes in data blocks of a given length and sums together the specified number of blocks, producing accumulated blocks of the same length but at a reduced rate.

AXI4-Stream Remapper 可用于在每个时钟 (PPC) 的不同像素要求之间重复映射视频像素。此外，该核还支持像素下降及像素重复特性。

AXI-4 Stream 至视频输出 LogiCORE™ IP 核可将 AXI4-Stream 接口信号转换成一个支持定时信号的标准并行视频输出接口。

Advanced, configurable and self-contained Baseline, Main and High profiles H.264 encoder supporting 4:2:0 and 4:2:2 sampling formats with up to 12-bit color depth.

This Bayer to RGB IP is highly resource optimized computer vision, thermal imaging IP which converts the Bayer images from cameras to RGB, so it can be used on video/image processing pipeline on FPGA.

Bayer-to-RGB converter used for the interpolation (demosaicing) of the bayer-mapped pixels from an image sensor color filter array (CFA).

10 Gb/s full HW stack UDP/IP Transmitter/Receiver IP block for high performance data transfers from embedded Ethernet based systems

10/100 or 1000 Mb/s full HW stack UDP/IP Transmitter/Receiver IP block for high performance data transfers from embedded Ethernet based systems.

The YantraVision Camera Link Receiver IP Core is complaint to Camera Link™ communication interface. Modes supported includes Base, Medium & Full Channel Link configurations.

The YantraVision Camera Link Receiver IP Core is complaint to Camera Link™ communication interface. Modes supported includes Base, Medium & Full Channel Link configurations.