System Integrated Logic Analyzer (System ILA)



The customizable System Integrated Logic Analyzer (System ILA) IP core is a logic analyzer which can be used to monitor the internal signals and interfaces of a design. The System ILA core includes many advanced features of modern logic analyzers, including Boolean trigger equations and edge transition triggers. The core also offers interface debug and monitoring capability along with AXI4-MM and AXI4-Stream protocol checking. Because the System ILA core is synchronous to the design being monitored, all design clock constraints that are applied to your design are also applied to the components of the System ILA core.


  • User-selectable number of probe ports and probe width
  • 多个探测端口,可组合为一个触发器条件
  • Debugging of any debuggable interface including AXI4-MM and Stream in a system created in IP Integrator
  • User-selectable AXI4-MM channel debug and AXI Data/Address width selection
  • Data and Trigger probe and interface type selection
  • BRAM estimation
  • AXI4-MM and AXI4-Stream Protocol Checking
  • IPI Support




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