Utility Reduced Logic

Overview

Xilinx provided utility function to simplify design in Vivado IP Integrator.

Product Description

The Utility Reduced Logic core applies a logic reduction function over an input vector to generate a single bit result. The core is intended as glue logic between peripherals. The logical operations supported are AND, OR, XOR and NOT.


Key Features and Benefits

  • Configurable size of the input vector
  • Configurable reduced logic operation on an input vector

Support

Documentation

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