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        SmartIOPS Solid State Drive Solution

        Xilinx partner SmartIOPS discusses their solid state drive product Data Engine T2 which is based on a 16nm NAND flash and incorporates their truRandom controller card which uses a Xilinx FPGA. The product can reach up to 1.7M IOPS per device and bandwidth can scale to 6.8GB/sec for random reads and nearly 4GB/sec for random writes with low latency. To see more, go to www.smartiops.com.

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        Database Acceleration Engine

        In this demo, rENIAC illustrates the use of Xilinx FPGAs in rENIAC’s Data Proxy Engine to accelerate Cassandra NoSQL databases without any software changes necessary. rENIAC’s distributed data proxy technology accelerates data stores (like NoSQL, SQL and Hadoop) and provides higher performance and significantly lower total cost of ownership. It delivers predictable 1/3-1/10 lower latency and up to 10x higher throughput. For more information or to start an evaluation, send an inquiry to: contact@reniac.com


        Everspin STT-MRAM Based NVMe Storage Accelerator

        在这个演示中，Everspin 展示了基于 STT-MRAM 的NVMe 存储加速器提供卓越的延迟确定性，为Apache Log4J 等应用提供低延迟写入缓冲。

        在 OFC 2016 演示 MoSys Bandwidth Engine 3

        Xilinx Alliance 成员 MoSys 在 OFC 2016 上演示其 Bandwidth Engine® 3 高速串行接口智能内存 IC 连接 Xilinx Zynq UltraScale+ MPSoC 平台。

        Versal LP/DDR4 2D Eye Scan

        使用 Vivado 2021.1 或更高版本实现的所有 Versal 集成内存控制器接口都支持 2D 眼图扫描功能。2D Eye Scan 可用于检查每个字节通道的健康状况，并允许图形比较以快速识别布局和开发板相关问题。 此功能无需更改设计，并自动包含在所有集成的 LP/DDR4 接口中。

        Zynq UltraScale+ MPSoC LPDDR4 2.4Gbps 内存接口 (英文版)

        本视频展示了 Zynq® UltraScale+™ MPSoC 处理系统中的硬控制器如何与 2.4Gbps LPDDR4 在压力下协同工作超过 48 个小时， 并实现低抖动及充足裕量。