产品描述
100GbE TCP Offloading Engine(TOE100G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE100G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for AMD FPGA. It helps you to reduce development time.
DesignGateway provides a demo file for AMD FPGA boards. You can evaluate TOE100G-IP core on a real board before purchasing.
主要特性与优势
- All pure hardware TCP/IP protocol stack for 100Gbit Ethernet
- Support IPv4 protocol
- Support one port connection (Support Multi-session by implementing multiple cores)
- Support both Server and Client mode (Passive/Active open and close)
- Support Jumbo frame
- Transmitted packet size aligned to 512-bit, transmitted data bus size
- Total receive data size aligned to 512-bit, received data bus size
- Simple data interface by standard FIFO interface at 512-bit data bus, and Simple control interface by single-port RAM interface
- AXI4 stream interface with AMD Ethernet MAC
- Provide free evaluation bit file for FPGA Development Kits
- Reference design is included in IP core product
特色技术文档
