TCPIP-1G/10G: 1G/10G TCP/IP Hardware Stack

  • 产品编号: TCPIP-1G/10G
  • 供应商: CAST, Inc.
  • Partner Tier: Elite Certified

产品描述

The TCPIP-1G/10G core implements a complete TCP/IP Hardware Protocol Stack. The core acts either as a server or a client and without any assistance from the host autonomously system, opens, maintains, and closes TCP connections. The system integrating the TCPIP-1G/10G core can configure network parameters and preferences by accessing its control registers, and the core is then able to receive and send data via streaming data interfaces. The core is highly configurable. The maximum number of simultaneous TCP sessions is configurable; it can be as high as 32,768 for devices like data servers, or as small as 1 for simpler edge devices. Further options include implementing a DHCP client, enabling or disabling the reassembly of out-of-order TCP packets data, and integrating a UDP hardware stack. Finally, users can choose the packet processing mode, either cut-through or store-and-forward. In cut-through mode, the payload data are delivered to the host system as they arrive without any internal packet buffering and before the packets’ integrity can be validated. As a result, the core operating in cut-through mode features extremely low latency and requires less memory, but it cannot reassemble out-of-order packets and may deliver data that will subsequently be marked as corrupted. Under the store-and-forward mode of operation, the core will always deliver verified, in-order packets but it will have higher latency and require more memory resources.


主要特性与优势

  • Optionally pre-integrated with AMD eMAC cores
  • Run-time programmable, IP and port filters
  • Optional Out-of-Order TCP packet assembly
  • Cut-through or store & forward processing
  • Implements VLAN, IPv4, ARP with Cache, ICMP (Ping Reply), TCP, and optionally UDP, IGMP, and DHCP
  • Autonomous and highly efficient TCP connection establishment, maintenance and teardown, retransmission, flow and congestion control
  • TCP server or client with up to 32k simultaneous TCP sessions
  • 10/100/1000, 2.5G, and 10G Ethernet Transmit and Receive

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VERSAL_AI_CORE Family XCVC1902 -2 Vivado ML 2021.2 0 31005 37 0 0 0 156
Kintex-UP Family XCKU19P -1 Vivado ML 2021.2 0 22420 38 0 0 0 156
Artix-UP Family XCAU25P -1 Vivado ML 2021.2 0 22422 38 0 0 0 156

IP 质量指标

综合信息

数据创建日期 Jun 24, 2023
当前 IP 修订号 1V00N00S00
当前修订日期已发布 Oct 13, 2022
第一版发布日期 Oct 13, 2022

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 1
可否提供参考? N

交付内容

可供购买的 IP 格式 Netlist, Source Code
源代码格式 Verilog
是否包含高级模型? N
提供集成测试台 Y
集成测试台格式 OVM System Verilog
是否提供代码覆盖率报告? Y
是否提供功能覆盖率报告? Y
是否提供 UCF? XDC
商业评估板是否可用? Y
评估板所用的 FPGA Kintex UltraScale
是否提供软件驱动程序? N
驱动程序的操作系统支持 -

实现方案

代码是否针对 Xilinx 进行优化? N
定制 FPGA 优化技术 None
所支持的综合软件工具及版本 Vivado Synthesis; Synplicity Synplify; Mentor Precision
是否执行静态时序分析? Y
AXI 接口 AXI4-Stream, AXI4-Lite
是否包含 IP-XACT 元数据? N

验证

是否有可用的文档验证计划? Executable and documented plan
测试方法 Both
断言 N
收集的覆盖指标 Functional, Code
是否执行时序验证? N
可用的时序验证报告 N
所支持的仿真器 Mentor Questa; Cadence NC-Sim; Mentor ModelSIM; Synopsys VCS

硬件验证

在 FPGA 上进行验证 Y
所使用的硬件验证平台 Kintex US
已通过的行业标准合规测试 N
是否提供测试结果? N