产品描述
The SPMI-CTRL core implements a highly featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus. It supports the latest version (v2.0) of the MIPI-SPMI specification, and is suitable for the implementation of either master or slave nodes in an SPMI bus.
The core is designed to minimize the software load on the host processor. Once configured, the core requires no assistance from the host to initialize the bus, connect to bus or disconnect from the bus, grant access of the bus, execute incoming SPMI commands, generate ACK/NACK responses, and check address and data parity. Although the core only expects the host to provide the outgoing SPMI commands, it provides thorough status information to the host.
Integration of the core is extremely simple.
主要特性与优势
- Small and Low Power: Less than 900 LUTs for either a master or a slave core, and direct serial clock usage to minimize switching activity when idle
- Easy Integration: Directly bridges SPMI and AHB bus address space, and allows register access via 32-bit AMBA™ 2 APB bus
- Run-time Debugging: Broadcasts SPMI bus state and device state, detects and reports errors, and can optionally captures all traffic in the SPMI bus
- Low Host Overhead: Host is only required to initialize registers after a reset and define outgoing commands and arbitration levels
- MIPI-SPMI v2.0 Master or Slave: Supports High Speed (HS) and Low Speed (LS) device classes, all commands and all arbitration levels.
特色技术文档
