Aurora 64B/66B

概述

产品描述

免费的LogiCORE™ IP 设计可以实现在Xilinx FPGA 中使用多吉比特收发器

Aurora 是为轻松实现 Xilinx 收发器而设计的 LogiCORE™ IP 核,同时其提供了轻量级用户接口,设计人员可以在此基础上构建串行链接。Aurora 64B/66B 是一个面向高速串行通信的可扩展的轻量级链路层协议。该协议规范是开放型规范,可按需提供。Xilinx 器件 IP Catalog 中的 IP 可免费使用。

Aurora 通常用于要求构建低成本、高数据速率、可扩展、灵活的串行数据通道的应用中。您可轻松使用其简单的成帧结构来压缩现有协议中的数据,并且其电气要求符合商品设备的规范。Aurora 可用于提高性能,且无需高昂的 FPGA 资源成本、软件重开发或借助外部物理基础架构。

应用
可以在任何需要串行点对点连接功能的应用中使用 Aurora 64B/66B。实例应用包括:

  • 芯片间的链接。以极少的 FPGA 资源成本显著地降低了 PCB 上的跟踪计数。实例:线卡、多器件分区、高速 ASIC-FPGA 连接
  • 开发板间和背板链接。 使用现有电缆、连接器和背板来提高系统吞吐量。实例:短距离光学和 ATCA 背板。
  • 数据流应用。无限多个帧使用随机空闲插入方式轻松通过 Aurora 通道进行数据传输。实例:低开销的数据单元传输和视频流。
  • 单向连接。 Aurora 单工通道可在一个方向实现低成本、高速的串行链接。实例:视频数据分流和远程数据传输。

主要功能与优势

  • 通用数据通道支持从 500 Mb/s 到 400 Gb/s 以上的吞吐量
  • 支持多达 16 个连续绑定的 7 系列 GTX/GTH、AMD UltraScale™ GTH/GTY 或 AMD UltraScale+™ GTH/GTY 或 AMD Versal™ GTY/GTYP/GTM 收发器
  • 符合 Aurora 64B/66B 协议规范 v1.3(64B/66B 编码)
  • 其资源成本低,并且传输开销也非常低 (仅为 3%)
  • 简单易用的 AXI4-Stream 组帧及流程控制接口
  • 可自动初始化和维护通道
  • 全双工或单工工作
  • 用户数据的 32 位循环冗余校验 (CRC)
  • 新增单工自动链路恢复特性支持
  • 支持 RX 极性倒转
  • 高位优先/低位优先 AXI4-Stream 用户接口
  • 完全兼容的 AXI4-Lite DRP 接口
  • 可配置 DRP、INIT 时钟
  • GTREFCLK 及内核 INIT_CLK 的单端/差分时钟选项

资源利用率


技术支持

技术文档

主要资料

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Results 1-14 of 14
Document
文件类型: Data Sheets
The LogiCORE IP Aurora 64B/66B core implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex-5 FXT and TXT and Virtex-6 LXT, SXT, and HXT devices.
Document
文件类型: Data Sheets
The LogiCORE IP Aurora 64B/66B core supports the AMBA protocol AXI4-Stream user interface. It implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in applicable Virtex-6 LXT, SXT, and HXT, Kintex-7, and Virtex-7 devices. This document contains information about the AXI4 version of the core.
Webpage
文件类型: Product Guide
Describes the Aurora 64B/66B link layer protocol, which is a scalable, lightweight, high data rate protocol for high-speed serial communication. The protocol is open and can be implemented using AMD FPGA technology.
Document
文件类型: Reference Guides
This specification describes the Aurora 64B/66B protocol. Aurora is a lightweight link-layer protocol that can be used to move data point-to-point across one or more high-speed serial lanes.
Document
文件类型: User Guides
This user guide describes the function and operation of the LogiCORE IP Aurora 64B/66B v4.1 core and provides information about designing, customizing, and implementing the core.
Document
文件类型: User Guides
The LogiCORE IP Aurora 64B/66B core implements the Aurora 64B/66B protocol using the high-speed serial GTX or GTH transceivers in Virtex-5 FPGA FXT/TXT and Virtex-6 FPGA LXT/SXT/HXT families.
Document
文件类型: User Guides
Aurora 64B/66B bus functional model (ABFM 64B/66B) models the Aurora 64B/66B protocol as defined by Aurora 64B/66B Protocol Specification v1.1 (SP011). It is used for verifying an Aurora 64B/66B protocol implementation design which is referred to as device under test (DUT).
Document
文件类型: User Guides
This user guide provides instructions for migrating from the Xilinx LogiCORE IP Aurora 8B/10B core to the Aurora 64B/66B core in a Virtex-5 FPGA. This guide also describes the function and and operation of these cores and the differences between them, and provides information about using the cores.
Document
文件类型: User Guides
The LogiCORE IP Aurora 64B/66B core supports the AMBA protocol AXI4-Stream user interface. The LogiCORE IP Aurora 64B/66B v7.1 User Guide provides information for generating a LogiCORE IP Aurora 64B/66B core using Virtex-7 and Kintex-7 FPGA GTX transceivers and Virtex-6 FPGA GTX/GTH transceivers.
Document
文件类型: Application Notes
This application note details the steps required to configure the Aurora 64B66B core with Vivado Design Suite and to validate core operation using VIO and ILA cores to probe signals.
Document
文件类型: Application Notes
This application note explains the steps required to validate the LogiCORE IP Aurora 64B/66B core in simplex mode on the Kintex-7 FPGA KC705 Evaluation Kit.
Document
文件类型: Application Notes
Demonstrates real-time video traffic across two 7 series FPGA evaluation boards. Also demonstrates the capabilities of the LogiCORE IP AXI Chip2Chip Bridge core using the LogiCORE IP Aurora 64B/66B core as the Physical Layer (PHY).
Document
文件类型: Application Notes
Aurora 64B66B is a scalable, lightweight, high data rate, link-layer protocol for high-speed serial communication. Aurora is designed to enable easy implementation of Xilinx transceivers using an intuitive wizard interface. The Aurora protocol specification is open and available upon request.
Document
文件类型: Application Notes
This application note explains the steps required to validate the Xilinx LogiCORE IP Aurora 64B/66B IP core working at 10.3125 Gb/s serial line rate and configured as a 16-lane link on the Virtex®-7 FPGA VC7203 Characterization Kit.
Results 1-14 of 14