产品描述
The Rambus DSC v1.2b Decoder IP Core implements video stream decompression functionality compliant with the VESA Display Stream Compression (DSC) v1.2(b) standard.
The DSC algorithms enable visually lossless compression for high-definition applications in the broadcast video, pro A/V, automotive, medical, and consumer electronics industries. Applications include video, graphics and display processors, video transport, display monitors, televisions, and DSC standard compliance test and measurement equipment.
The VESA DSC compression standard is compatible with several transport standards including MIPI DSI 1.2, VESA Embedded DisplayPort 1.4a, DisplayPort 1.4a, and HDMI 2.1.
DSC technology enables high resolutions such as 4K (4096x2160), 5K (UHD+), and 8K (FUHD) at higher color depths.
Please contact Rambus for further information.
主要特性与优势
- VESA Display Stream Compression (DSC) 1.2a compliant
- Supports all DSC 1.2a mandatory and optional encoding mechanisms
- Backward compatible to DSC v1.1
- Configurable maximum display resolution up to 8K (FUHD)
- 8, 10, and 12 bits per video component
- YCbCr and RGB video output format
- 4:4:4, 4:2:2, and 4:2:0 native coding
- Resilient to bitstream corruption
- 3 pixels / clock internal processing architecture in 4:4:4
- 6 pixels / clock internal processing architecture in 4:2:2 and 4:2:0
- Parameterizable number of parallel slice decoder instances (1, 2, 4, 8) to adapt to the capability of the technology and target display resolutions used
- Automatic run time configuration of the number of parallel slice decoder instances in use
- AXI-Stream interfaces for easy integration in IP integrator
- AXI-Lite interface for register access
- PPS 128 bytes block decoding
- Compliant solution for DisplayPort 1.4 or HDMI 2.1
- Compatibility for slices per line requirements
- Supports flexible usage models and design architecture (inline decoding or panel frame buffer decoding)
