DLIN - LIN Bus Controller

产品描述

The DLIN is a soft core of the Local Interconnect Network (LIN). This interface is a serial communication protocol, designed primarily to be used in automotive applications. Compared to CAN, LIN is slower, but thanks to its simplicity, is much more cost effective. Our Core is ideal for a communication in intelligent sensors and actuators, where the bandwidth and versatility of CAN is not required. The DLIN core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as master or slave LIN node, depending on a work mode, determined by the microprocessor/microcontroller. DCD's controller supports transmission speed between 1 and 20kb/s, which allows it to transmit and receive LIN messages compatible to LIN 1.3. LIN 2.1 and the newest 2.2. The reported information status includes the type and condition of transfer operations being performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). Our Core includes programmable timer, which allows to detect timeout and synchronization error. The DLIN is described at RTL level, empowering the target use in FPGA and ASIC technologies.


主要特性与优势

  • “Break-in-data” support
  • Extended error detection
  • Time-out detection
  • Master and Slave work mode
  • Data rate between 1Kbit/s and 20 Kbit/s
  • Automatic Re-synchronization
  • Automatic LIN Header handling
  • Conforms with LIN 1.2, LIN 2.1 and LIN 2.2 specification

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU13P -2 Vivado ML 2023.1 Y 495 783 0 0 0 0 512
KINTEX-7 Family XC7K410T -1 Vivado ML 2023.1 Y 495 838 0 0 0 0 285
ARTIX-7 Family XC7A200T -3 Vivado ML 2023.1 Y 495 830 0 0 0 0 263
Zynq-7000 Family XC7Z010 -3 Vivado 2019.1 Y 0 620 0 0 0 0 263
Spartan 6 Family XC6SLX16 -3 ISE 14.4 Y 167 511 0 0 0 0 127
VIRTEX-U Family XCVU080 -3 Vivado 2015.4 Y 0 539 0 0 0 0 330
KINTEX-U Family XCKU035 -3 Vivado 2015.4 Y 0 516 0 0 0 0 330

IP 质量指标

综合信息

数据创建日期 Nov 15, 2023
当前 IP 修订号 1.03
当前修订日期已发布 Dec 13, 2013
第一版发布日期 Sep 12, 2008

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 2
可否提供参考? N

交付内容

可供购买的 IP 格式 Netlist, Source Code
源代码格式 VHDL, Verilog
是否包含高级模型? N
提供集成测试台 Y
集成测试台格式 VHDL, Verilog
是否提供代码覆盖率报告? Y
是否提供功能覆盖率报告? N
是否提供 UCF? UCF
商业评估板是否可用? N
是否提供软件驱动程序? Y
驱动程序的操作系统支持 -

实现方案

代码是否针对 Xilinx 进行优化? N
定制 FPGA 优化技术 -
所支持的综合软件工具及版本 Xilinx XST; Synplicity Synplify; Mentor Precision
是否执行静态时序分析? Y
是否包含 IP-XACT 元数据? N

验证

是否有可用的文档验证计划? Executable and documented plan
测试方法 Both
断言 N
收集的覆盖指标 Code, Functional, Assertion
是否执行时序验证? Y
可用的时序验证报告 Y
所支持的仿真器 Cadence NC-Sim; Cadence IUS; Mentor ModelSIM

硬件验证

在 FPGA 上进行验证 Y
所使用的硬件验证平台 FPGA
已通过的行业标准合规测试 N
特定的合规测试 own
测试日期 Sep 11, 2008
是否提供测试结果? Y