Wired Communications Intellectual Property

Comcores 10G Ethernet Switch IP core is a highly configurable and size optimized implementation of a non-blocking switch that allows continuous transfers between 10G Ethernet ports. The switch supports up to twenty 10G XGMII ports where each port provides a native interface for Ethernet PHY devices....

10G Ethernet IP 核能实现通过 IP 集成器提供的 1 步和 2 步 1588 硬件时戳。

Comcores compact high speed Ethernet switch delivers state of the art performance offering four 25 Gbps ports and twelve 10 Gbps ports. The switch supports MAC learning and aging, VLAN 802.1Q, multicast, broadcast as well as IEEE1588 transparency. It implements store-and-forward switching approach i...

Comcores 10M/100M/1G/2.5G TSN MAC provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Preemption, 802.3br Interspersing Express Traffic, 802.1AS Timing and Synchronization and 802.1Qbv Enhancements for Scheduled Traffic. The TSN MAC enables d...

Comcores Lite Ethernet Switch (LES) IP core is a size-optimized and highly configurable implementation of a non-blocking ring switch that allows continuous transfers between up to 73 ports Ethernet ports via 1 Gbps GMII interfaces. The switch supports MAC learning and implements store-and-forward sw...

Comcores 1G/10G Lite Ethernet Switch (LES) IP core is a highly configurable and size optimized implementation of a non-blocking ring switch that allows continuous transfers between up to 4 10G Ethernet ports and 40 1G Ethernet ports. The switch supports MAC learning, VLAN 802.1Q, multicast and broad...

1G/10G/25G Switching Ethernet Subsystem 可在 1G 或 10G 物理编码子层/物理层 (PCS/PHY) 之间交换以太网媒体访问控制器 (MAC)。该 IP 核可通过 Vivado® 设计套件作为加密寄存器传输层 (RTL) 提供。

1K Session Full TCP&UDP Offload Engine with Integrated 10G EMAC. Full Line rate throughput across all Simultaneous Sessions

概述 ... 支持 RS（544、514）KP4 编码和解码 支持符号错误统计（包括每信道统计） 资源利用率 ... 技术支持 器件系列: ... Versal AI Core Series

The single use project license for Xilinx LogiCORE PCI132 Spartan Interface.

AMD 400G 高速以太网 (400G HSEC) 子系统通过物理编码子层 (PCS) 提供 400G 以太网介质访问控制 (MAC)，包括 Reed-Solomon 前向纠错 (RS-FEC) 或支持 RS-FEC 的独立 400GAUI-16 PCS/PMA。

LogiCORE™ 400G IEEE 802.3bs Reed-Solomon Forward Error Correction IP 核可实现 Reed-Solomon 前向纠错 (RS-FEC) 子层。

Xilinx 高速以太网 LogiCORE®（HSEC）是面向 40Gbps 和 100Gbps 以太网的高性能、灵活的 IEEE 802.32012 实现方案。

Interlaken 是一款可扩展的芯片至芯片互联协议，可实现从 10Gbps 到 150Gbps 的传输速度。

LogiCORE™ Initiator/Target for PCI ™/PCI-X ™ 支持 PCI-X v2.0 Mode 1 规范，可加快高吞吐量通信系统的开发速度。

LogiCORE™ IP 7 系列 FPGA 收发器向导自动化创建 HDL 封装，以配置 AMD 7 系列 FPGA 片上收发器。

TMC’s AES encryption / decryption IP core is validated by "NIST CAVP". We offer high quality solution using our original computer algorithm, [ DMNA ]. It processes at high speed, so it can be used high-speed LAN systems and other fields.

LogiCORE AMM Master Bridge IP 核将 Avalon Master 端点转换为 AXI Master。该 IP 允许您使用参数设置匹配 Avalon Master 端点的属性，从而实现与 AXI 的无缝接口。

The New Wave Design and Verification (New Wave DV) ARINC-818 core provides a complete hardware IP solution for the ARINC-818 protocol. The core provides full specification compliance, hardware-based container processing, and offload of frame handling including: ARINC-818 Container offload, hardwar...

Aurora 是为轻松实现 AMD 收发器而设计的 LogiCORE™ IP 核，同时其提供了轻量级用户接口，设计人员可以在此基础上构建串行链接。

Aurora is a LogiCORE IP designed to enable easy implementation of Xilinx transceivers while providing a light-weight user interface on top of which designers can build a serial link.

LogiCORE™ AXI Firewall IP 旨在防止 AXI DMA 免遭挂起以及其协议违反下游的威胁，否则这可能会导致主机崩溃。

AXI4 PCIe 核提供事务处理等级转换功能，可将 AXI4 命令转换为 PCIe TLP 数据包，将PCIe 请求转换为 AXI4 命令。

面向 JTAG 接口的 AXI 协议转换 ... 设计工具: Vivado Design Suite 技术文档 主要资料 Vivado IP 发布说明 Default Default 标题 文件类型 日期

Xilinx 通用串行总线 2.0 高速设备支持高级微控制器总线架构高级 eXtensible 接口 (AXI)，可使用最少的资源实现 USB 对用户设计的连接。

10 Gb/s full HW stack UDP/IP Transmitter/Receiver IP block for high performance data transfers from embedded Ethernet based systems

10/100 or 1000 Mb/s full HW stack UDP/IP Transmitter/Receiver IP block for high performance data transfers from embedded Ethernet based systems.

BSCAN to JTAG Converter 是一款可定制的内核，不仅可生成 JTAG 事务处理，而且还可驱动 JTAG 信号。

注意：只为带本地风扇的有源卡报告风扇速度，不支持对被动卡 ... 技术文档 主要资料 Vivado IP 发布说明 Default Default 标题 文件类型 日期

产品描述 ... 支持 Vivado IP integrator ... 不仅支持高达 992 位的所有密钥位宽，而且还支持高达 1024 位的 ... 支持 UltraRAM (URAM) 和 blockRAM 实现方案。