AXI Video DMA (AXI VDMA)

概述

产品描述

AXI Video Direct Memory Access (AXI VDMA) 核是一款软 AMD IP 核,可在内存与 AXI4-Stream 类视频目标外设之间提供高带宽直接内存访问该内核通过独立异步读写通道运算提供高效的 2D DMA 运算。初始化、状态、中断及管理寄存器均可通过 AXI4-Lite 从接口进行访问。


主要功能与优势

  • 符合 AXI4 规范
  • 支持 32、64、128、256、512 和 1024 位的主要 AXI4 数据位宽
  • 主要 AXI4-Stream 数据位宽支持 8 的倍数,最高达 1024 位
  • 可选数据重新对齐引擎
  • 可选 Genlock 同步
  • 独立异步通道操作
  • AXI4-Stream 接口时钟的动态时钟频率变化
  • 帧前进或错误重复可选
  • 支持达 32 帧的缓冲区
  • 支持达 64 位的 AXI4 地址空间

资源利用率


技术支持

技术文档

主要资料

文件类型
Clear
Results per page
  • 30
  • 60
  • 120
  • 150
Default Default 标题Arrow UpArrow Down 文件类型Arrow UpArrow Down 日期Arrow UpArrow Down
List LayoutList
Results 1-11 of 11
Document
文件类型: Data Sheets
The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core for use with the Xilinx Embedded Development Kit (EDK). The AXI VDMA engine provides high-bandwidth direct memory access between memory and AXI Stream-video type target peripherals. This document contains information about the AXI4 version of the core.
Document
文件类型: Data Sheets
The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. This document contains information about the AXI4 version of the core.
Webpage
文件类型: Product Guides
This core is a soft core providing high-bandwidth direct memory access between memory and AXI4-Stream-video type target peripherals. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface.
Document
文件类型: Application Notes
This application note covers design principles for obtaining high performance from the Zynq-7000 AP SoC memory interfaces, from AXI master interfaces implemented in the programmable logic (PL), and from the ARM Cortex-A9 processor(s).
Document
文件类型: Application Notes
Demonstrates real-time video traffic across two 7 series FPGA evaluation boards. Also demonstrates the capabilities of the LogiCORE IP AXI Chip2Chip Bridge core using the LogiCORE IP Aurora 64B/66B core as the Physical Layer (PHY).
Document
文件类型: Application Notes
This application note demonstrates how to use the LogiCORE™ IP AXI Video DMA (VDMA) core in a typical video application.
Document
文件类型: Application Notes
Bridging XSVI to AXI4-Stream for video buffering in Spartan-6 and Virtex-6 devices.
Associated File(s):
Document
文件类型: Application Notes
This application note demonstrates how to create a basic DDR3 MPMC design using ISE Logic Edition tools including Project Navigator (ProjNav) and CORE Generator software.
Associated File(s):
Document
文件类型: Application Notes
This application note covers the design considerations of a system using the performance features of the LogiCORE IP Advanced eXtensible Interface (AXI) Interconnect core.
Associated File(s):
Document
文件类型: Application Notes
This application note covers the design considerations of a video system using the performance features of the LogiCORE IP Advanced eXtensible Interface (AXI) Interconnect core,This application note covers the design considerations of a video system using the performance features of the LogiCORE IP Advanced eXtensible Interface (AXI) Interconnect core.
Associated File(s):
Document
文件类型: Application Notes
This application note demonstrates the creation of video systems by using Xilinx native video IP cores to process configurable frame rates and resolutions in Kintex-7 FPGAs. The reference design is targeted for the Kintex-7 FPGA XC7K325TFFG900-2 on the Xilinx KC705 evaluation board.
Associated File(s):
Results 1-11 of 11