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Connectivity

Building your Design Becomes Easier and Faster

Xilinx builds an array of connectivity solutions to help you design faster.  With IP interface solutions that allow you to connect from FPGA to various other chipsets and IP cores that help bridge logic internally within the FPGA, building your design becomes easier and faster.   Xilinx also offers several Development Boards to use together with these IP solutions.

External Connectivity

Spend more time differentiating your product while Xilinx builds the most popular connectivity IP solutions for you. With Ethernet solutions from 1M to 400G, PCI Express® from Gen1x1 to Gen3x16, and a range of other interface IPs that can run up to 25G, we will meet your bandwidth needs.

The major IP interface blocks that we support are below.  SW drivers accompany many of our IP solutions as well.

Major IP Interface Blocks Supported by Xilinx

Internal Connectivity

Xilinx offers multiple IP solutions for connecting different IP blocks within the FPGA logic. While there are many different protocols for external interfaces, Xilinx standardizes IP interconnect with the AXI4 protocol.

Both AXI Memory Mapped and AXI Stream can be used for moving data.

AXI Memory Mapped is used when address and control must be sent separately with data and each being sent on its own AXI bus.  AXI Stream is used when streaming high speed data with no burst limit and no separate address / control AXI bus. Xilinx also offers AXI Lite for control interfaces.

AXI SmartConnect
Latest high speed solution for connecting AXI Memory Mapped interfaces only.  Exclusively supported in our GUI based IP Interconnect application.

AXI Interconnect
First generation solution that connects AXI Memory Mapped and/or AXI Lite interfaces.  Supported in RTL and the GUI based IP Interconnect application.

AXI Stream Interconnect
High speed solution for connecting AXI Stream based interfaces.  Supported in RTL and the GUI based IP Interconnect application.

AXI DMA
Solution to connect AXI Stream and AXI Memory Mapped interfaces together.

DMA (Direct Memory Access) is a methodology to move data between different locations without the need of a processor to send the data.  A typical DMA has a processor or another intelligent controller to set up the source and destination of the data transfer but the DMA block handles the actual transfer of data Xilinx has a number of DMA IPs built for specific types of data movement and are set up primarily for these three areas of use:

  • PCIe DMA for moving data between system memory and any memory space mapped inside the FPGA                 
  • Embedded DMAs which are useful to move data inside the Zynq hard processor domain to various areas around the FPGA
  • Video DMA which is used to buffer data for video processing.
Application PCIe Embedded Video
IP Name DMA for PCIe AXI DMA AXI MCDMA AXI CDMA ZU+ DMA AXI VDMA
Typical Use Case Move data between x86 system memory and DDR4 memory attached to FPGA over a PCIe link Zynq to 10Gb Ethernet communication in programmable logic area Ethernet (1G/10G) to multiple DDR4 channels Zynq to BRAM communication in programmable logic area Zynq to DDR3 communication in processor area HDMI video data to DDR4 memory for format conversion
Interface PCIe to AXI Memory Mapped or AXI Stream AXI Stream to AXI Memory Mapped AXI Stream to (<= 8) AXI Memory Mapped interfaces AXI Memory Mapped to AXI Memory Mapped AXI Memory Mapped to Zynq US+ Processor AXI Stream to AXI Memory Mapped
Efficiency   S2MM: 75%
MM2S: 99%
S2MM: 75%
MM2S: 99%
99% 100%  
Performance (Gbps) 7GB/s S2MM: 215
MM2S: 280
S2MM: 230
MM2S: 300
280 25 4k 60fps
SW Drivers x86 based Linux Linux and Baremetal Linux and Baremetal Linux and Baremetal Linux and Baremetal Linux and Baremetal

Developer Zone

For FPGA designers looking to shorten design time and ensure scalability and re-use, Xilinx provides a comprehensive suite of solutions ranging from C-based design abstractions to IP plug-and-play to address bottlenecks in hardware development, system-level integration, and implementation.

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