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乘法器操作很重要,并且广泛用于 DSP 应用。Achieving maximum implementation efficiency and clock performance is therefore critical to DSP systems and frequently presents a significant challenge to hardware engineers.

The Multiplier LogiCORE™ simplifies this challenge by abstracting away FPGA device specifics, while maintaining the required maximum performance and resource efficiency. The multiplier is able to generate parallel multipliers, and constant coefficient multipliers, both with differing implementation styles. Furthermore, with the aid of instantaneous resource estimation, hardware engineers can rapidly select the optimal solution for their system.

This IP provides fine control over the latency (pipelining) of the multipliers (purely combinatorial to fully pipelined) and symmetric rounding implemented in the DSP48 slice. Fully pipelined implementations enable maximum clock frequency performance


  • 2's complement signed/unsigned fixed point multiplier
  • Parallel and fixed constant coefficient multipliers
  • Supports Inputs ranging 1 to 64 bits wide and outputs ranging from 1 to 128 bits wide with any portion of the full product selectable
  • Supports symmetric rounding to infinity when using the DSP Slice
  • 瞬时资源估算
  • Optional Clock Enable, and Synchronous Clear
  • VHDL behavioral models
  • 瞬时资源估算
  • For use with Vivado® IP Catalog and Xilinx System Generator for DSP





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