乘法累加器

简介

产品描述

The Multiply Accumulator IP accepts two operands, a multiplier and a multiplicand, and produces a product (A*B=Prod) that is added/subtracted to the previous adder/subtracter result (S=S+/-Prod). This product value can be loaded with assertion of Bypass (S=Prod). The Multiply Adder IP is implemented using Xtreme DSP™ slices and operates on signed or unsigned data.


主要特性与优势

  • Supports multiplier inputs ranging from 1 to 31 bits unsigned or 2 to 32 bits signed and an output width ranging from 1 to 79 bits unsigned or 2 to 80 bits signed 
  • Latency can be set for optimal speed or the minimal amount of pipelining allowed "Latency = 1" (accumulation register required)
  • 瞬时资源估算
  • For use with Xilinx CORE Generator™

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