RAM-based Shift Register

概述

产品描述

AMD 基于 RAM 的 LogiCORE™ 移位寄存器 IP 核可使用 AMD FPGA 器件中所提供 slice LUT 的 SRL16/SRL32 模式生成快速、小巧、类似于 FIFO 的寄存器、延迟线路或时间偏移缓冲器。实现支持 SRL16/SRL32 的移位寄存器,可显著节省资源和功耗。该 IP 既支持固定长度移位寄存器,也支持可变长度移位寄存器。


主要功能与优势

  • 使用切片 LUT 的 SRL16 / SRL32 模式来生成快速和小型 FIFO 类型的寄存器或延迟线。
  • 用户可创建固定长度或可变长度的移位寄存器
  • 对于可变长度移位寄存器,可优化速度或资源
  • 对于可变长度移位寄存器,输出寄存器具有可选的时钟使能和同步控制

资源利用率


技术支持

技术文档

主要资料

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Document
文件类型: Data Sheets
The LogiCORE IP AXI Interrupt Controller (AXI INTC) concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. This AXI INTC core is designed to interface with the AXI4-Lite protocol.
Document
文件类型: Product Guides
Describes the AXI Interrupt Controller (AXI INTC) core which receives multiple interrupt inputs from peripheral devices and merges them to a single interrupt output to the system processor.
Associated File(s):
Document
文件类型: Application Notes
This application note demonstrates a simple embedded display system using the LogiCORE IP AXI Thin Film Transistor (TFT) core on the Kintex-7 FPGA KC705 Evaluation Kit.
Document
文件类型: Application Notes
Demonstrates real-time video traffic across two 7 series FPGA evaluation boards. Also demonstrates the capabilities of the LogiCORE IP AXI Chip2Chip Bridge core using the LogiCORE IP Aurora 64B/66B core as the Physical Layer (PHY).
Document
文件类型: Application Notes
This application note demonstrates how to use the LogiCORE™ IP AXI Video DMA (VDMA) core in a typical video application.
Results 1-5 of 5